Low temperature chemical mechanical polishing of dielectric materials

ABSTRACT

The present invention is an improved apparatus and process for chemical mechanical polishing layers which have a low dielectric constant (K). The present invention lowers the temperature of the material having a low dielectric constant and then polishes that material at the lower temperature. By lowering the temperature of the low K material the hardness or stiffness of the material is improved making it easier to polish and resulting in a more planar surface.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to the field of semiconductor devices, andmore specifically, to a process and apparatus for chemical mechanicalpolishing.

[0003] 2. Background Information

[0004] Integrated circuits manufactured today are made up of literallymillions of active devices such as transistors and capacitors formed ina semiconductor substrate. These active devices are formed andinterconnected in an elaborate system of layers. A considerable amountof effort in the manufacture of modern complex, high density multilevelinterconnections is devoted to the planarization of the individuallayers of the interconnect structure. Nonplanar surfaces create pooroptical resolution of subsequent photolithographic processing steps.Poor optical resolution prohibits the printing of high densityinterconnect metal lines. Another problem with nonplanar surfacetopography is the step coverage of subsequent metallization layers. If astep height is too large there is a serious danger that open circuitswill be created. Planar interconnect surface layers are a must in thefabrication of modern high density integrated circuits.

[0005] To ensure planar topography, various planarization techniqueshave been developed. One approach, known as chemical mechanicalpolishing, employs polishing to remove protruding steps formed along theupper surface of interlayer dielectrics (ILDs). Chemical mechanicalpolishing is also used to “etch back” conformally deposited metal layersto form planar plugs or vias. FIG. 1 illustrates a typical chemicalmechanical polisher 100. As shown, a substrate (or wafer) 110 is held bya carrier 120. Carrier 120 presses wafer 110 against polishing pad 130that is attached to polishing platen 140. Polishing pad 130 is coveredwith an active slurry 150 and polishing platen 140 rotates in onedirection while carrier 120 rotates in the opposite direction. Therotational motion, surface of the polishing pad, and slurry act togetherto polish or planarize the surface of wafer 110 at ambient temperature(i.e. room temperature).

[0006] However, as semiconductor devices become smaller and more densechemical mechanical polishing is causing some problems with newermaterials used to fabricate current semiconductor devices. Prior artmaterials used in conjunction with chemical mechanical polishing havebeen relatively hard and/or stiff materials such as oxides, polysilicon,etc. As a result, chemical mechanical polishing processes have beenoptimized for these materials.

[0007] New materials, such as materials with low dielectric constantsare being used in order to reduce the RC Time Constant in currentsemiconductor devices. The RC Time Constant is the fundamental limit ofa microprocessor caused by the capacitance between the metal lines ofthe microprocessor. There are two things which determine the RC TimeConstant: the resistance of the metal lines themselves and thecapacitance of the dielectric materials.

[0008] Silicon dioxide, which is widely used as a dielectric materialhas a dielectric constant (k) of approximately k=4. However, byswitching to materials with lower dielectric constants, for example inthe range of approximately k=2−3, several advantages may be obtained.The use of low k polymers have been found reduce the RC Time Constantdue to a decreased capacitance and therefore increase the speed of thedevice. The use of low k materials have also been found to improve powerdissipation, and reduce crosstalk noise between metal lines.

[0009] Unfortunately, low k materials tend to be more polymers which aremore plastic like materials. Therefore, when polishing such low kmaterials in chemical mechanical polishing, because they are plastic,they tend to bend and/or deform causing bad results and bad uniformityduring planarization.

[0010]FIG. 2 illustrates a low k material after planarization with priorart chemical mechanical polisher and polishing method. As shown, low kmaterial 210 was deposited above metal lines 220 and substrate 200.Since low k material 210 is somewhat plastic it deformed during thechemical mechanical polishing process. As illustrated, because low kmaterial 210 deformed during polishing the top surface is not uniformand is not evenly planarized.

[0011] Thus, what is needed is a chemical mechanical polisher andpolishing process that will enable the planarization of low k materialswith good results and uniformity.

SUMMARY OF THE INVENTION

[0012] The present invention is a method and apparatus for planarizingby lowering the temperature of the material to be polished and polishingthat material at the lowered temperature.

[0013] Additional features and benefits of the present invention willbecome apparent from the detailed description, figures, and claims setforth below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention is illustrated by way of example and notlimitation in the accompanying figures in which:

[0015]FIG. 1 illustrates a typical chemical mechanical polisher used inthe prior art.

[0016]FIG. 2 illustrates a low k material after planarization with priorart chemical mechanical polisher and polishing method.

[0017]FIG. 3 illustrates a chemical mechanical polisher of the presentinvention.

[0018]FIG. 4 illustrates a low k material after planarization with thechemical mechanical polishing apparatus and process of the presentinvention.

DETAILED DESCRIPTION

[0019] A Process and Apparatus for Low Temperature Chemical MechanicalPolishing of Dielectric Materials is disclosed. In the followingdescription, numerous specific details are set forth such as specificmaterials, process parameters, equipment, etc. in order to provide athorough understanding of the present invention. It will be obvious,however, to one skilled in the art that these specific details need notbe employed to practice the present invention. In other instances, wellknown materials or methods have not been described in detail in order toavoid unnecessarily obscuring the present invention.

[0020] The present invention is an improved apparatus and process forchemical mechanical polishing layers which have a low dielectricconstant (k). The present invention lowers the temperature of thematerial having a low dielectric constant and then polishes thatmaterial at the lower temperature. By lowering the temperature of thelow k material the hardness (or stiffness) of the material is improvedmaking it easier to polish and resulting in a more planar surface.

[0021] It should be noted that, the process steps and structuresdescribed below do not form a complete process flow for manufacturingintegrated circuits. The present invention can be practiced inconjunction with integrated circuit fabrication techniques currentlyused in the art, and only so much of the commonly practiced processsteps are included as are necessary for an understanding of the presentinvention. The figures representing portions of an integrated circuitduring fabrication are not drawn to scale, but instead are drawn so asto illustrate the important features of the invention.

[0022] It should also be noted that, reference to a substrate mayinclude a bare or pure semiconductor substrate, with or without doping,a semiconductor substrate with epitaxial layers, a semiconductorsubstrate incorporating one or more device layers at any stage ofprocessing, other types of substrates incorporating one or moresemiconductor layers such as substrates having semiconductor oninsulator (SIO) devices, or substrates for processing other apparati anddevices such as flat panel displays, multichip modules, etc.

[0023] As stated in the background of the invention, low k dielectricmaterials, such as polymers, are being used in order to reduce the RCTime Constant and to improve the performance of semiconductor devices.Such low k materials however deform and/or bend in prior art chemicalmechanical polishing (CMP) processes and apparati. Some examples of lowk materials are polyarimatic ethers (PAEs) and paralene, both of whichexhibit dielectric constants of approximately k=2.5.

[0024] In order to improve the planarization of low k materials thepresent invention lowers the temperature of the low k material duringthe CMP process. By deliberately lowering the temperature of the low kmaterials the materials become harder (or stiffer) which improves theresults of polishing. As stated in the background of the invention priorart CMP processes are performed at ambient (or room) temperature. Thepresent invention lowers the temperature of the CMP process belowambient (or room) temperature. For example, the temperature of the low kmaterial may be lowered to a temperature in the range of approximately5-65° C. It should be noted, however, that the temperature will bedependent upon the properties of the particular material being used.

[0025]FIG. 3 illustrates a chemical mechanical polisher 200 as used inan embodiment of the present invention. As shown, a substrate (or wafer)310 is held by a carrier 320. Carrier 320 includes a chiller 360 tolower the temperature of wafer 310 and thereby lower the temperature ofthe low k material on the wafer 310. Chiller 360 may be a temperaturecontrolled loop which circulates a cooled liquid or gas through thecarrier. The lowered temperature of wafer 310 increases the hardness (orstiffness) of the low k material deposited thereon in order to improvethe planarization of the CMP process.

[0026] Chemical mechanical polisher 200, as shown, also has a polishingplaten 340 which includes a chiller 370. Chiller 370 is used to reducethe temperature of the polishing pad 330 thereby reducing thetemperature of the CMP process. When carrier 310 presses wafer 310against polishing pad 330 the lowered temperature of the polishing padhelps to lower the temperature of the low k material deposited on wafer310. Thus, increasing the hardness (or stiffness) of the low k materialduring the CMP process.

[0027] An additional benefit of the embodiment having a chiller in thepolishing platen is that the hardness of the polishing pad 330 may beincreased by reducing the temperature of the polishing pad 330. In theprior art it was necessary to physically change the pad material inorder to change the hardness of the polishing pad 330.

[0028] It should be noted that although chemical mechanical polisher ofthe present invention is depicted in FIG. 3 as having chillers in boththe carrier and polishing platen the present invention may be performedby having the chiller in either the carrier or polishing platen and itis not necessary to include a chiller in both. It should also be notedthat other methods and apparati for lowering the temperature of the lowk material may be used in place of or in conjunction with the chiller(or chillers) illustrated in FIG. 3. For example, a temperaturecontrolled slurry 350 (i.e. a slurry with a lowered temperature) may beused to lower the temperature of the polishing process and increase thehardness or stiffness of the low k material.

[0029]FIG. 4 illustrates a low k material after planarization with thechemical mechanical polishing apparatus and process of the presentinvention. As shown, low k material 410 was deposited above metal lines420 and substrate 400. Since, with the use of the present invention, lowk material 410 is harder (or stiffer) than it would be at roomtemperature it does not deform during CMP. As illustrated, because low kmaterial 410 was harder during polishing with the present invention thetop surface is uniform and is more evenly planarized.

[0030] Thus, a Process and Apparatus for Low Temperature ChemicalMechanical Polishing of Dielectric Materials has been described.Although specific embodiments, including specific equipment, parameters,methods, and materials have been described, various modifications to thedisclosed embodiments will be apparent to one of ordinary skill in theart upon reading this disclosure. Therefore, it is to be understood thatsuch embodiments are merely illustrative of and not restrictive on thebroad invention and that this invention is not limited to the specificembodiments shown and described.

What is claimed is:
 1. A method for planarization comprising: loweringthe temperature of a material to be polished; and polishing saidmaterial at said lowered temperature.
 2. The method as described inclaim 1 wherein said material has a low dielectric constant in the rangeof approximately k =1-3.
 3. The method as described in claim 1 whereinsaid material is a low k polymer.
 4. The method as described in claim 3wherein said material is selected from the group consisting of:paralene, PAE, and a combination thereof.
 5. The method as described inclaim 1 wherein said lowered temperature is less than ambienttemperature.
 6. The method as described in claim 1 wherein said step ofpolishing is a chemical mechanical polishing process.
 7. A polishercomprising: a wafer carier, said carrier having a first chiller; apolishing pad; and a polishing platen.
 8. The polisher as described inclaim 7 wherein said first chiller is a temperature controlled loopusing a chilled liquid.
 9. The polisher as described in claim 7 whereinsaid first chiller is a temperature controlled loop using a chilled gas.10. The polisher as described in claim 7 wherein said polishing platenhas a second chiller.
 11. The polisher as described in claim 10 whereinsaid second chiller is a temperature controlled loop using a chilledliquid.
 12. The polisher as described in claim 10 wherein said secondchiller is a temperature controlled loop using a chilled gas.
 13. Thepolisher as described in claim 7 further comprising a slurry deliverysystem, wherein said slurry delivery system delivers a temperaturecontrolled slurry to said polisher.
 14. A polisher comprising: a wafercarrier; a polishing pad; and a polishing platen, said platen having afirst chiller.
 15. The polisher as described in claim 14 wherein saidfirst chiller is a temperature controlled loop using a chilled liquid.16. The polisher as described in claim 14 wherein said first chiller isa temperature controlled loop using a chilled gas.
 17. The polisher asdescribed in claim 14 wherein said carrier has a second chiller.
 18. Thepolisher as described in claim 17 wherein said second chiller is atemperature controlled loop using a chilled liquid.
 19. The polisher asdescribed in claim 17 wherein said second chiller is a temperaturecontrolled loop using a chilled gas.
 20. The polisher as described inclaim 14 further comprising a slurry delivery system, wherein saidslurry delivery system delivers a temperature controlled slurry to saidpolisher.